TP-LINK TL-MR3020 v1.x

Overview

 * TP-LINK TL-MR3020 v3.x (v3/v3.20)
 * CPU: MediaTek MT7628NN @575MHz WiSoC
 * Flash: GigaDevice GD25Q64BSIG (8MB)
 * RAM: Zentel A3R12E40DBF-8E (64MB)
 * WLAN: 802.11bgn 2T2R (2.4GHz)
 * LAN: 1x FE, USB: 1x USB 2.0 port
 * PCB ID: 2050500974

Links of Interest

 * TP-LINK TL-MR3020 on the OpenWrt wiki

Notes on JTAG
The EJTAG interface AR9331 is different from the ones on most chips:
 * First of all, the Jtag pins are multiplexed with GPIOs, GPIO11 must be pull high to bootstrap the debug interface.
 * Pressing the SW2 switch while powering on the unit should take care of this as it is connected to GPIO11.


 * The second problem is that U-Boot will disable EJTAG, even if it was enabled by pulling GPIO11 high during power up.
 * To workaround this, a jumper can be added between the CS pin on the flash and CPU.


 * And last problem is that TP-Link does not provide test points, pads or pins for the Jtag interface.

OpenOCD
This sequence will be needed to initiate PLL and RAM:

Pictures
Retail Images