Qualcomm Atheros QCA7500

The QCA7500 HPAV2 Compliant MAC/PHY Transceiver is a System-on-Chip (SoC) designed to bridge multi-stream Ethernet content from a powerline network to an Ethernet 802.3 network. Examples include high and standard definition television (HDTV, SDTV), and other digital multimedia file sharing and data applications. The powerline communications (PLC) specific MAC manages network admission and service flows to maximize the quality of service (QoS) over the powerline network.

QCA7500 is a product of Qualcomm Technologies, Inc., and/or its subsidiaries. Product license agreement

Specifications

Wi-Fi

Encryption: AES-CCMP, AES-GCMP

Ethernet

Peak PHY Rate: 10 Mbps, 100 Mbps, 1000 Mbps

Peak Speed: Up to 1300 Mbps

Standards: IEEE 1905.1, IEEE 1900, IEEE 1901

Powerline Communication Standards: Home Plug 1.0, Home Plug AV2

Powerline Configuration: MIMO, SISO

Powerline Frequency Bands: 30 MHz, 67.5 MHz

Memory

Speed: 533 MHz, 400 MHz

Type: DDR3, DDR2

Flash

Density: 4 MB

Type: NOR

Interface: SPI

Interfaces

Supported Interfaces: RGMII, 1x ADC, RMII, UART, SPI, 1x DAC

General Purpose I/Os: 10

Layers: MAC, PHY

Analog-To-Digital Converter (ADC)

Number of Interfaces: 1

Digital-To-Analog Converter (DAC)

Number of Interfaces: 1

Package

Type: DRQFN

Size: 12 × 12 mm