TP-LINK TL-ER5120
| Gigabit Load Balance Broadband Router | |
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| Homepage | Product page |
|---|---|
| Wikipedia | TP-Link |
| WikiDevi.wi-cat.ru | TP-LINK TL-ER5120 |
| 3rd Party Firmware | |
| dd-wrt | Status Unknown |
| OpenWrt | Status Unknown |
| Tomato any flavor | Incompatible |
| Platform | |
| Brand • Model • Rev | TP-LINK TL-ER5120 v1.3 |
| Board ID | 2021500120 |
| Type | router |
| CPU1 | Cavium CN5010 |
| CPU1 Type | MIPS64 OCTEON Plus |
| CPU1 Speed | 500 MHz |
| Flash1 Chip | STMicro M29W640GB-70NA6 |
| Flash1 Size | 8 MiB 8,388,608 B <br />65,536 Kib <br />8,192 KiB <br />64 Mib <br />0.00781 GiB <br /> |
| RAM1 Size | 128 MiB 134,217,728 B <br />1,048,576 Kib <br />131,072 KiB <br />1,024 Mib <br />0.125 GiB <br /> |
| RAM1 Chip | SK hynix H5PS5162GFR-Y5C x 2 |
| ETH chip1 | Cavium CN5010 |
| Switch | Broadcom BCM53115S |
| Ethernet Port Count |
1-1GbE-WAN 4-1GbE-LAN |
| Wired Standard | IEEE 802.3i/3u/3ab |
| Expansion IF types | none specified |
| Power | 100-240 VAC ~ 50/60 Hz, 0.6 A |
| Connector type | C13 |
| Serial Port (UART) | yes, RJ45 console, (115200 8N1) |
| JTAG Port | yes, 14-pad header, J1 |
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Flags: | |
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Additional chips | |
| Other | |
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Default IP address: 192.168.0.1 | |
| Retail | |
| Availability | End of Life |
| Country of manuf | China |
For a list of all currently documented Broadcom chipsets with specifications, see Broadcom.
For a list of all currently documented Cavium (Star) SoC's with specifications, see Cavium.
For a list of all currently documented TP-LINK devices with specifications, see TP-LINK.
Overview
Specifications
- Cavium OCTEON CN50XX Single Core MIPS64
- RISC 64-bit @500MHz Embedded Processors
- 16KB Instruction Cache
- 8KB Data Cache
- 2KB Write Cache
- 128KB L2 Cache