ZyXEL XGS1250-12

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12-Port Web-Managed Multi-Gigabit Switch
Homepage Product page
WikiDevi.wi-cat.ru ZyXEL XGS1250-12
3rd Party Firmware
dd-wrt Status Unknown
OpenWrt Supported
Tomato any flavor Incompatible
Gargoyle Status Unknown
Platform
Brand • Model • Rev ZyXEL XGS1250-12 rev A1
Board ID 2976966401
CPU1 checkY Realtek RTL9302B
CPU1 Type MIPS 34Kc
CPU1 Speed 800 MHz
Flash1 Chip Macronix MX25L12833F
Flash1 Size 16 MiB 16,777,216 B <br />131,072 Kib <br />16,384 KiB <br />128 Mib <br />0.0156 GiB <br />
RAM1 Size 128 MiB 134,217,728 B <br />1,048,576 Kib <br />131,072 KiB <br />1,024 Mib <br />0.125 GiB <br /> (DDR3 SDRAM)
RAM1 Chip Winbond W613GU6MB-12
ETH chip1 Realtek RTL9302B
ETH chip2 Realtek RTL8218D
ETH chip3 Aquantia AQR113C
ETH chip4 Aquantia AQR113C
ETH chip5 Aquantia AQR113C
Switch Realtek RTL9302B
Ethernet Port Count 12-1GbE
Ethernet connector 8P8C
Wired Standard IEEE 802.3i/3u/3ab
Port-based vlan yes
Auto-MDIX supported
Jumbo frame yes
Switch Class managed

Ethernet OUI: none specified

Expansion IF types SFP+
SFP ports 1
Stock bootloader U-Boot
Power 12 VDC, 2 A
Connector type barrel
Serial Port (UART) yes, 4-pin header, 3.3V TTL, (115200 8N1)
Other
Manuf/OEM/ODM Delta Networks
3rd Party Firmware Support OpenWrt • (List | Dev | DLs)

Additional chips
Serial GPIO/LED Display Controller;Realtek;RTL8231;;1;

Retail
(Est.) release date November 2021
 Switch brandSwitch2 brand
ZyXEL XGS1250-12Realtek
ZyXEL XGS1250-12 rev B1Realtek

For a list of all currently documented Aquantia SoC's with specifications, see Aquantia.
For a list of all currently documented Realtek chipsets with specifications, see Realtek.

For a list of all currently documented ZyXEL devices with specifications, see ZyXEL.

Overview

The XGS1250-12 is a 11 + 1-port Multi-Gigabit L3 switch. It has 8 Gigabit ports, three 2.5/5/10GBit Ethernet ports and one SFP+ 10GBit uplink cages.

Power is supplied via a 12V 2A standard barrel connector. At the right side behind the grid is UART serial connector. A Serial header can be connected to from the outside of the switch trough the airvents with a standard 2.54mm header. Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial connection is via 115200 baud, 8N1.

Links of Interest

Flashing

Flashing OpenWrt

Target: realtek
Subtarget: rtl930x
Package architecture: mips_24kc
Supported Since Commit
Support started version: 22.03.0
Current supported version: 25.12.1
LAN Hardware: Realtek RTL9302B
LAN Comment: Realtek RTL8218D 8x Gb Phy, 4x Aquantia AQR113c 10Gb Phy (Supports 100M/1G/2.5G/5G/10G)
WLAN Hardware: none
WLAN Comment: No WLAN
Installation method(s):
See git-commit
Recovery method(s):
U-Boot web recovery
Recovery Comment:
Wipe firmware region to activate web recovery
Comment:
SFP+ works since Version 24.10
git • >>
realtek: Add support for ZxXEL XGS1250-12 Switch
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with
8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and
1 SFP+ module slot.

Hardware:
 - RTL9302B SoC
 - Macronix MX25L12833F (16MB flash)
 - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
 - RTL8231 GPIO extender to control the port LEDs
 - RTL8218D 8x Gigabit PHY
 - Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs
 - SFP+ 10GBit slot

Power is supplied via a 12V 2A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.

A reset button is accessble through a hole in the front panel

At the time of this commit, all ethernet ports work under OpenWRT,
including the various NBaseT modes, however the 10GBit SFP+ slot is not
supported.

Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
  to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
  > fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
  > sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
  value as is - without 'rtk network on' the switch will fail to initialise
  the network.

Web recovery
------------
The XGS1250-12 has a handy web recovery that will load when U-boot does
not find a bootable kernel. In case you would like to trigger the web
recovery manually, partially overwrite the firmware partition with some
zeroes:

  # dd if=/dev/zero of=/dev/mtd5 bs=1M count=2

If you have serial connected you'll see U-boot will start the web recovery
and print it's listening on 192.168.1.1, but by default it seems to be on
the OEM default IP for the switch - 192.168.1.3. The web recovery only
listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI.

Return to stock
---------------
You can flash the ZyXEL firmware images to return to stock:

  # sysupgrade -F -n XGS1250-12_Firmware_V1.00(ABWE.1)C0.bix

Notes

Board Configuration • >>

------------------ Board Configuration ------------------

****************************
 ZYXEL XGS1250-12
****************************
============================
 Board GPIO
============================
Device  Pin  Direction  Default  Current  Purpose
------- ---- ---------- -------- -------- --------
INT     0    OUT        0        0        
INT     1    IN         1        1        FAN_CONTROL
INT     6    IN         1        0        HW_VER_BIT1
INT     7    IN         1        1        HW_VER_BIT0
INT     11   OUT        0        0        FAN_EN
INT     15   OUT        0        0        TX_DIS_P11
INT     16   IN         0        1        SFP_Present_P11
INT     17   IN         0        1        SFP_LOS_P11
INT     20   IN         0        0        TX_FAULT_P11
INT     21   OUT        1        1        RESET_PHY
INT     22   IN         1        1        RST_BTN_OUT

============================
 Board Configuration
============================
====== Port ==================
Type        Usr  Phy     Media       Speed          Duplex   Attr
----------- ---- ------- ----------- -------------- -------- -------
1000M       1    (0) 0   Copper      (A) ALL        Auto     0      
1000M       2    (0) 1   Copper      (A) ALL        Auto     0      
1000M       3    (0) 2   Copper      (A) ALL        Auto     0      
1000M       4    (0) 3   Copper      (A) ALL        Auto     0      
1000M       5    (0) 4   Copper      (A) ALL        Auto     0      
1000M       6    (0) 5   Copper      (A) ALL        Auto     0      
1000M       7    (0) 6   Copper      (A) ALL        Auto     0      
1000M       8    (0) 7   Copper      (A) ALL        Auto     0      
10G         9    (0) 24  Copper      (A) ALL        Auto     0      
10G         10   (0) 25  Copper      (A) ALL        Auto     0      
10G         11   (0) 26  Copper      (A) ALL        Auto     0      
10G         12   (0) 27  Fiber       (F) 10G        (F) Full 0      


====== Fiber =================
Fiber Port Number: 1

------------ Fiber Detect
LPort  Present  MediaChg  OE Status              LOS Status
------ -------- --------- ---------------------- ----------------------
11     OE       None      Enabled  (GPIO:INT_16) Enabled  (GPIO:INT_17)

------------ Fiber Optical
LPort  I2C DEV  I2C TYPE  ID    Delay   SCK    SDA
------ -------- --------- ----- ------- ------ ------
11     2        8 BITS    0x50  50      INT_8  INT_10

------------ Fiber TX Disable
LPort  Method
------ ------
11     GPIO(INT_15)


====== Button ================

------------ Reset Button
GPIO: INT_22
Timer: 3(sec)  Action: Reboot
Timer: 6(sec)  Action: Restore Factory


====== Led ===================
SYSTEM
  ON [ASIC(G)]
  OFF [ASIC(G)]
  BLINK [ASIC(G)]
Port
  ON [ASIC(P)]
  ON C2 [ASIC(P)]
  OFF [ASIC(P)]
  AUTO [ASIC(P)]


====== Reset =================
Type: GPIO
GPIO: INT_21


====== WatchDog ==============
Type: REG