WatchGuard AP200

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abgn (AN600)
Indoor (Plenum) Access Point
WikiDevi.wi-cat.ru WatchGuard AP200
3rd Party Firmware
dd-wrt Status Unknown
OpenWrt Supported
Tomato any flavor Incompatible
Gargoyle Status Unknown
Platform
BrandModelRev WatchGuard AP200 v1.0.2
FCC ID (fcc.io) U2M-CAP4200AG
FCC ID (fcc.report) U2M-CAP4200AG
IC ID 3616C-CAP4200AG
Board ID 7016A0507001
Type access point
CPU1 checkY Atheros AR9344
CPU1 Type MIPS 74Kc
CPU1 Speed 533 MHz 32-bit
Flash1 Chip Macronix MX25L12845EMI-10G
Flash1 Size 16 MiB 16,777,216 B <br />131,072 Kib <br />16,384 KiB <br />128 Mib <br />0.0156 GiB <br /> (SPI NOR)
RAM1 Size 128 MiB 134,217,728 B <br />1,048,576 Kib <br />131,072 KiB <br />1,024 Mib <br />0.125 GiB <br /> (DDR2 SDRAM)
RAM1 Chip Nanya NT5TU32M16DG-AC x 2
ETH chip1 Atheros AR9344
ETH chip2 Atheros AR8035-A
Ethernet Port Count 1-1GbE-LAN
Wired Standard IEEE 802.3i/3u/3ab

802dot11 OUI: 00:90:7F (24 E, 17 W)
Ethernet OUI: 00:90:7F (24 E, 17 W)

Stock bootloader U-Boot 1.1.4
Stock FW OS Linux 2.6.31
Expansion IF types none specified
PoE 802.3at, 802.3af, standard
Power 12 VDC, 1.25 A
Connector type barrel
5.5 mm (OD)
2.1 mm (ID)
9.5 mm (LEN)
Serial Port (UART) yes, 4-pin header, populated, 3.3V TTL, (115200 8N1)

Flags:
PoE in

Additional chips
1-Channel Photocoupler;LiteOn;LTV-817;;1;
150V N-Channel MOSFET;Vishay Siliconix;Si4848DY;;3;
5GHz Power Amplifier w/Power Detector;SiGe;SE2537L;;2;
IEEE 802.3at PoE Interface and DC/DC Controller;TI;TPS23754;;1;
2.4GHz High-Gain Power Amplifier;Silicon Storage Technology;SST12LP15A;;2;

Other

Default IP address: 192.168.1.1
the IP 192.168.1.1 is used by 1355 additional devices
of which 2 are WatchGuard devices

Manuf/OEM/ODM Senao CAP4200AG
3rd Party Firmware Support OpenWrt • (List | Dev | DLs)
Retail
Availability End of Life
End of Life date 01 July 2019
FCC approval date 28 November 2012
Newegg 12K-012P-00005
ASIN B00DPODN9S
Country of manuf Taiwan
Radio 1
Chip1 Atheros AR9344
Wireless interface OUI 00:90:7F
Antenna Connector Type U.FL (internal)
MIMO status 2x2:2
Wireless Standard IEEE 802.11a/n
802.11n up to 300 Mbps
802.11a up to 54 Mbps
WiFi Operating Frequency 5 GHz
Radio 2
Chip1 Atheros AR9382
Wireless interface OUI 00:90:7F
Antenna Connector Type U.FL (internal)
MIMO status 2x2:2
Wireless Standard IEEE 802.11b/g/n
802.11n up to 300 Mbps
802.11g up to 54 Mbps
802.11b up to 11 Mbps
WiFi Operating Frequency 2.4 GHz
 FCC ID
AirTight Networks SS-300-AT-C-55U2M-CAP4200AG
PowerCloud Systems CAP324U2M-CAP4200AG
Senao CAP4200AGU2M-CAP4200AG

For a list of all currently documented Atheros (QCA) chipsets with specifications, see Atheros.

For a list of all currently documented WatchGuard devices with specifications, see WatchGuard.

300 Mbps - 2SS 5GHz 802.11n (40MHz chan.),
300 Mbps - 2SS 2.4GHz 802.11n (40MHz chan.) = AN600 class

Overview

"7016A0507001 Ver: 1.00" is silkscreened on the board in the FCC photos.

Hardware specification

  • CPU: Atheros AR9344 MIPS 74K (@560MHz)
  • Memory: 128MB (SDRAM) DDR2
  • Storage: 8MB SPI NOR Flash
  • WiFi: Atheros AR9344 (802.11an)
Atheros AR9382 (802.11bgn)
  • Network: 1x Gigabit Ethernet ports
  • Power: 12V, 1.25A via barrel or 802.3af/at PoE

Links of Interest

Hardware Guide

Flashing

Flashing OpenWrt

Target: ath79
Subtarget: generic
Package architecture: mips_24kc
Supported Since Commit
Support started version: 23.05.0
Current supported version: 25.12.0
LAN Comment: Atheros AR8035-A GbE Phy
WLAN Hardware: Atheros AR9344, Atheros AR9382
WLAN Comment: 2.4Ghz 2x2:2 MIMO, 5Ghz 2x2:2 MIMO
Installation method(s):
see git-commit
Recovery method(s):
see git-commit
git • >>
ath79: add support for Senao WatchGuard AP200
FCC ID: U2M-CAP4200AG

WatchGuard AP200 is an indoor wireless access point with
1 Gb ethernet port, dual-band wireless,
internal antenna plates, and 802.3at PoE+

this board is a Senao device:
the hardware is equivalent to EnGenius EAP600
the software is modified Senao SDK which is based on openwrt and uboot
including image checksum verification at boot time,
and a failsafe image that boots if checksum fails

**Specification:**

  - AR9344 SOC		MIPS 74kc, 2.4 GHz WMAC, 2x2
  - AR9382 WLAN		PCI card 168c:0030, 5 GHz, 2x2, 26dBm
  - AR8035-A EPHY	RGMII GbE with PoE+ IN
  - 25 MHz clock
  - 16 MB FLASH		mx25l12805d
  - 2x 64 MB RAM
  - UART console        J11, populated
  - GPIO watchdog       GPIO 16, 20 sec toggle
  - 4 antennas          5 dBi, internal omni-directional plates
  - 5 LEDs              power, eth0 link/data, 2G, 5G
  - 1 button            reset

**MAC addresses:**

  Label has no MAC
  Only one Vendor MAC address in flash at art 0x0

  eth0 ---- *:be art 0x0 -2
  phy1 ---- *:bf art 0x0 -1
  phy0 ---- *:be art 0x0 -2

**Installation:**

  Method 1: OEM webpage

    use OEM webpage for firmware upgrade to upload factory.bin

  Method 2: root shell

    It may be necessary to use a Watchguard router to flash the image to the AP
    and / or to downgrade the software on the AP to access SSH
    For some Watchguard devices, serial console over UART is disabled.

  NOTE: DHCP is not enabled by default after flashing

**TFTP recovery:**

  reset button has no function at boot time
  only possible with modified uboot environment,
  (see commit message for Watchguard AP300)

**Return to OEM:**

  user should make backup of MTD partitions
  and write the backups back to mtd devices
  in order to revert to OEM reliably

  It may be possible to use sysupgrade
  with an OEM image as well...
  (not tested)

**OEM upgrade info:**

  The OEM upgrade script is at /etc/fwupgrade.sh

  OKLI kernel loader is required because the OEM software
  expects the kernel to be no greater than 1536k
  and the factory.bin upgrade procedure would otherwise
  overwrite part of the kernel when writing rootfs.

**Note on eth0 PLL-data:**

  The default Ethernet Configuration register values will not work
  because of the external AR8035 switch between
  the SOC and the ethernet port.

  For AR934x series, the PLL registers for eth0
  can be see in the DTSI as 0x2c.
  Therefore the PLL registers can be read from uboot
  for each link speed after attempting tftpboot
  or another network action using that link speed
  with `md 0x1805002c 1`.

  The clock delay required for RGMII can be applied
  at the PHY side, using the at803x driver `phy-mode`.
  Therefore the PLL registers for GMAC0
  do not need the bits for delay on the MAC side.
  This is possible due to fixes in at803x driver
  since Linux 5.1 and 5.3

**Note on WatchGuard Magic string:**

  The OEM upgrade script is a modified version of
  the generic Senao sysupgrade script
  which is used on EnGenius devices.

  On WatchGuard boards produced by Senao,
  images are verified using a md5sum checksum of
  the upgrade image concatenated with a magic string.
  this checksum is then appended to the end of the final image.

  This variable does not apply to all the senao devices
  so set to null string as default

Pictures

User Images